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W42C31-09
Spread Spectrum Frequency Timing Generator
Features
* Maximized EMI suppression using Cypress's Spread Spectrum technology * Generates a spread spectrum copy of the provided input * Integrated loop filter components * Operates with a 3.3V or 5V supply * Low-power CMOS design * Available in 8-pin SOIC (Small Outline Integrated Circuit) to pass increasingly difficult EMI testing without resorting to costly shielding or redesign. In a system, not only is EMI reduced in the various clock lines, but also in all signals which are synchronized to the clock. Therefore, the benefits of using this technology increase with the number of address and data lines in the system. The Simplified Block Diagram shows a simple implementation. Table 1. Frequency Spread Selection W42C31-09 FS1 0 0 1 1 FS0 0 1 0 1 Input Frequency (MHz) 30 to 55 30 to 55 30 to 55 30 to 55 Output Frequency (MHz) fIN 0.625% fIN 1.25% fIN 2.5% fIN -3.75%
Overview
The W42C31-09 incorporates the latest advances in PLL spread spectrum frequency synthesizer techniques. By frequency modulating the output with a low-frequency carrier, EMI is greatly reduced. Use of this technology allows systems
Simplified Block Diagram
Pin Configuration
VDD CLKIN NC GND FS1 1 2 3 4
SOIC W42C31-09 8 7 6 5 SSON# CLKOUT FS0 VDD
Oscillator or Reference Input
W42C31-09
Spread Spectrum Output (EMI suppressed)
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 January 25, 2000, rev. *B
W42C31-09
Pin Definitions
Pin Name CLKOUT CLKIN NC SSON# FS0:1 VDD GND Pin No. 7 1 2 8 6, 4 5 3 Pin Type O I I I I P G Pin Description Output Modulated Frequency: Frequency modulated copy of the unmodulated input clock. External Reference Frequency Input No Connect: This pin must be left unconnected. Spread Spectrum Control (Active LOW): Pulling this input signal LOW turns the internal modulation waveform on. This pin has an internal pull-down resistor. Frequency Selection Bit 0: These pins select the frequency spreading characteristics. Refer to Table 1. These pins have internal pull-up resistors. Power Connection: Connected to 3.3V or 5V power supply. Ground Connection: This should be connected to the common ground plane. Frequency Selection With SSFTG In Spread Spectrum Frequency Timing Generation, EMI reduction depends on the shape, modulation percentage, and frequency of the modulating waveform. While the shape and frequency of the modulating waveform are fixed, the modulation percentage may be varied. Using frequency select bits (FS1:0 pins), various spreading percentages can be chosen (see Table 1). A larger spreading percentage improves EMI reduction. However, large spread percentages may either exceed system maximum frequency ratings or lower the average frequency to a point where performance is affected. For these reasons, spreading percentages between 0.5% and 2.5% are most common. The W42C31 features the ability to select from various spread spectrum characteristics. Selections specific to the W42C31-09 are shown in Table 1. Other spreading characteristics are available (see separate data sheets) or can be created with a custom mask. Also, other devices in the W42C31 family offer frequency multiplication in addition to the spread spectrum function. This will allow the use of less expensive fundamental mode crystals.
Functional Description
The W42C31-09 uses a phase-locked loop (PLL) to frequency modulate an input clock. The result is an output clock whose frequency is slowly swept over a narrow band near the input signal. The basic circuit topology is shown in Figure 1. The input reference signal is divided by Q and fed to the phase detector. A signal from the VCO is divided by P and fed back to the phase detector also. The PLL will force the frequency of the VCO output signal to change until the divided output signal and the divided reference signal match at the phase detector input. The output frequency is then equal to the ratio of P/Q times the reference frequency. (Note: For the W42C31-09 the output frequency is equal to the input frequency.) The unique feature of the Spread Spectrum Frequency Timing Generator is that a modulating waveform is superimposed at the input to the VCO. This causes the VCO output to be slowly swept across a predetermined frequency band. Because the modulating frequency is typically 1000 times slower than the fundamental clock, the spread spectrum process has little impact on system performance.
VDD
Clock Input Freq. Divider Q Phase Detector Charge Pump
Reference Input
VCO
Post Dividers
CLKOUT (EMI suppressed)
Modulating Waveform Feedback Divider P
PLL
GND
Figure 1. System Block Diagram (Concept, not actual implementation)
2
W42C31-09
Spread Spectrum Frequency Timing Generation
The benefits of using Spread Spectrum Frequency Timing Generation are depicted in Figure 2. An EMI emission profile of a clock harmonic is shown. Contrast the typical clock EMI with the Cypress Spread Spectrum Frequency Timing Generation EMI. Notice the spike in the typical clock. This spike can make systems fail quasi-peak EMI testing. The FCC and other regulatory agencies test for peak emissions. With spread spectrum enabled, the peak energy is much lower (at least 8 dB) because the energy is spread out across a wider bandwidth. Modulating Waveform The shape of the modulating waveform is critical to EMI reduction. The modulation scheme used to accomplish the maximum reduction in EMI is shown in Figure 3. The period of the modulation is shown as a percentage of the period length along the X axis. The amount that the frequency is varied is shown along the Y axis, also shown as a percentage of the total frequency spread. Cypress frequency selection tables express the modulation percentage in two ways. The first method displays the spreading frequency band as a percent of the programmed average output frequency, symmetric about the programmed average frequency. This method is always shown using the expression fCenter XMOD% in the frequency spread selection table. The second approach is to specify the maximum operating frequency and the spreading band as a percentage of this frequency. The output signal is swept from the lower edge of the band to the maximum frequency. The expression for this approach is fMAX - XMOD%. Whenever this expression is used, Cypress has taken care to ensure that fMAX will never be exceeded. This is important in applications where the clock drives components with tight maximum clock speed specifications. SSON# Pin An internal pull-down resistor defaults the chip into a spread spectrum mode. The SSON# pin enables the spreading feature when set LOW. The SSON# pin disables the spreading feature when set HIGH (VDD).
5 dB /div
EMI Reduction
S S FT G
Typ ical C lo ck
Amplitude (dB )
Spread Spectrum Enabled
NonSpread Spectrum
-S S %
F req uen cy S p an (M Hz )
+SS%
Figure 2. Typical Clock and SSFTG Comparison
100% 80% 60% 40% 20% 0% -20% -40% -60% -80% -100%
Frequency Shift
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
Time
Figure 3. Modulation Waveform Profile
3
100%
W42C31-09
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions Parameter VDD, VIN TSTG TA TB PD Description Voltage on any pin with respect to GND Storage Temperature Operating Temperature Ambient Temperature under Bias Power Dissipation above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Rating -0.5 to +7.0 -65 to +150 0 to +70 -55 to +125 0.5 Unit V C C C W
DC Electrical Characteristics: 0C < TA < 70C, VDD = 3.3V 10%
Parameter IDD tON VIL (Logic Inputs) VIL (CLKIN) VIH (Logic Inputs) VIH (CLKIN) VOL VOH IIL IIH IOL IOH CI CI RP ZOUT Description Supply Current Power Up Time Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Current Input High Current Output Low Current Output High Current Input Capacitance Input Capacitance Input Pull-Up Resistor Clock Output Impedance IOL = 21.6 mA Note 2 Note 2 @ 0.4V, VDD = 3.3V @ 2.4V, VDD = 3.3V All pins except CLKIN CLKIN pin only 6 500 25 15 15 7 10
[1] [1]
Test Condition First locked clock cycle after Power Good
Min
Typ 18
Max 32 5 0.8 .4
Unit mA ms V V V V
2.4 2.8 0.4 2.5 -100 10 IOH = 31.5 mA
V V A A mA mA pF pF k
Notes: 1. Output driver is full CMOS. 2. Inputs FS1:0 have a pull-up resistor, Input SSON# has a pull-down resistor.
4
W42C31-09
DC Electrical Characteristics: 0C < TA < 70C, VDD = 5V 10%
Parameter IDD tON VIL (Logic Inputs) VIL (CLKIN) VIH (Logic Inputs) VIH (CLKIN) VOL VOH IIL IIH IOL IOH CI CI RP ZOUT Description Supply Current Power Up Time Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Current Input High Current Output Low Current Output High Current Input Capacitance Input Capacitance Input Pull-Up Resistor Clock Output Impedance IOL = 25.7mA IOH = 118.mA Note 2 Note 2 @ 0.4V, VDD = 5V @ 2.4V, VDD = 5V All pins except CLKIN CLKIN pin only 6 500 25 24 24 7 10 2.5 -100 10 0.7VDD 4.2 0.4 First locked clock cycle after Power Good Test Condition Min Typ 30 Max 45 5 0.15VDD 0.4 Unit mA ms V V V V V V A A mA mA pF pF k
AC Electrical Characteristics: TA = 0C to +70C, VDD = 3.3V10%
Symbol fIN fOUT tR tF tOD tID tJCYC Parameter Input Frequency Output Frequency Output Rise Time Output Fall Time Output Duty Cycle Input Duty Cycle Jitter, Cycle-to-Cycle Harmonic Reduction fout = 40 MHz, third harmonic measured, reference board, 15-pF load 8 Test Condition Input Clock Spread Off V, 15-pF load 0.8 - 2.4 V, 15-pF load 2.4 - 0.8 15-pF load 40 40 250 Min 30 30 Typ 40 40 2 2 Max 55 55 5 5 60 60 300 Unit MHz MHz ns ns % % ps dB
AC Electrical Characteristics: TA = 0C to +70C, VDD = 5V10%
Symbol fIN fOUT tR tF tOD tID tJCYC Parameter Input Frequency Output Frequency Output Rise Time Output Fall Time Output Duty Cycle Input Duty Cycle Jitter, Cycle-to-Cycle Harmonic Reduction fout = 40 MHz, third harmonic measured, reference board, 15-pF load 8 Test Condition Input Clock Spread Off V, 15-pF load 0.8 - 2.4 V, 15-pF load 2.4 - 0.8 15-pF load 40 40 250 Min 30 30 Typ 40 40 2 2 Max 55 55 5 5 60 60 300 Unit MHz MHz ns ns % % ps dB
5
W42C31-09
Application Information
Recommended Circuit Configuration For optimum performance in system applications the power supply decoupling scheme shown in Figure 4 should be used. VDD decoupling is important to both reduce phase jitter and EMI radiation. The 0.1-F decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the inReference Input NC GND
creased trace inductance will negate its decoupling capability. The 10-F decoupling capacitor shown should be a tantalum type. For further EMI protection, the VDD connection can be made via a ferrite bead, as shown. Recommended Board Layout Figure 5 shows a recommended 2-layer board layout.
W42C31-09
1 2 3 4
8 7 6 5
R1 VDD Clock Output
C1 0.1 F
5V or 3.3V System Supply
FB
C2 10 F Tantalum
Figure 4. Recommended Circuit Configuration
C1 = C2 =
High frequency supply decoupling capacitor (0.1-F recommended). Common supply low frequency decoupling capacitor (10-F tantalum recommended). Match value to line impedance Ferrite Bead
Via To GND Plane
R1 = FB =
=
G
Reference Input NC R1
Clock Output
G
C1 G C2 G
FB
Power Supply Input (3.3V or 5V)
Figure 5. Recommended Board Layout (2-Layer Board)
Ordering Information
Ordering Code W42C31 Document #: 38-00799-B Freq. Mask Code 09 Package Name G Package Type 8-pin Plastic SOIC (150-mil)
6
W42C31-09
Package Diagram
8-Pin Small Outline Integrated Circuit (SOIC, 150-mil)
(c) Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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